A memory device package typically includes a semiconductor memory die encased in a plastic or ceramic casing, and package contacts that enable the device package to be electrically connected to a printed circuit board (PCB). As shown in FIG. 1A, a memory device assembly 100a has multiple memory device packages 102 mounted to a PCB 104. Each of the memory device packages 102 includes package contacts 106 having a pin assignment 107. The PCB 104 includes metal traces 108 (shown schematically) that electrically interconnect the address pins A[2], A[8], A[7], and A[9] on one of the memory device packages 102 to the same address pin on the other. The traces 108 also connect the address pins to a memory controller device (not shown) mounted to the PCB 104.
FIG. 1B shows a memory device assembly 100b in which the memory device packages 102 are attached to opposite sides of the PCB 104. In this type of assembly, the traces 108 are located on both sides of the PCB 104, and can be interconnected by vias (not shown) that extend through the board. One advantage of the assembly 100b is that it has a reduced footprint since both memory device packages 102 are located generally within the same planform area of the board. A challenge with assembly 100b, however, is that since the lower device package is flipped upside down, its address pins are arranged in the reverse order of the address pins of the upper device package. Consequently, the traces that interconnect each pair of corresponding outer address pins A[7] and A[8] are relatively longer than the traces that connect each pair inner address pins A[2] and A[9]. The longer traces accordingly have a larger electrical resistance, and this can reduce signal quality. Additionally, the longer traces can cause timing skew, since they have a longer signal path than the shorter traces.